When internal circuits of a semiconductor integrated circuit device is supplied with power and the internal circuits are simultaneously supplied with power, transient current noise increases and generates power noise. Therefore, semiconductor integrated circuits are provided with a plurality of power switch circuits arranged between power supplies and internal circuits. The power switch circuits sequentially become conductive to suppress the peak value of the transient current. The operation of such power switch circuits must be stabilized.
FIG. 5 shows an example of a prior art semiconductor integrated circuit device including power switch circuits SW1 to SWn. The power switch circuits SW1 to SWn are arranged between a high potential power supply VDD and a plurality of logic circuits 1. Each logic circuit 1 is supplied with power VSS. When each of the power switch circuits SW1 to SWn becomes conductive, each logic circuit 1 is supplied with the power VDD.
The power switch circuits SW1 to SWn sequentially become conductive in response to a control signal E provided from a power control circuit. That is, a control signal E is input to an input terminal EI of the power switch circuit SW1 in the initial stage. After a predetermined delay time elapses, the control signal E is provided from an output terminal EO to the power switch circuit SW2 in the next stage.
In the same manner, the power switch circuit SW2 becomes conductive in response to the control signal E input to the input terminal EI. After a predetermined delay time elapses, the control signal E is provided from an output terminal EO to the power switch circuit SW3 in the next stage.
FIG. 6 shows the structure of the power switch circuits SW1 to SWn. The power switch circuits SW1 to SWn have identical structures. Thus, the power switch circuit SW1 will now be described.
The control signal E is input to the input terminal EI and provided to the gate of a P-channel MOS transistor T1. Therefore, when an L level signal is input to the input terminal EI, the transistor T1 becomes conductive and the power VDD, which is supplied to a terminal PS, is supplied from a terminal PD to the logic circuit 1.
The signal EI input to the input terminal E is output from the output terminal EO through a time difference generation circuit 2. The time difference generation circuit 2 includes, for example, an even number of series-coupled inverter circuits 3 as shown in FIG. 7.
In such a configuration, each of the power switch circuits SW1 to SWn transfers the control signal E after the delay time set by the time difference generation circuit 2 elapses. Thus, the transistors T1 sequentially become conductive as the control signal E and the power VDD is sequentially supplied to the logic circuits 1.
In the semiconductor integrated circuit device that includes the power switch circuits SW1 to SWn, the power switch circuits SW1 to SWn sequentially become conductive, and the plurality of logic circuits 1 are sequentially supplied with the power VDD. This suppresses the transient current.
However, the timing difference in which the power switch circuits SW1 to SWn become conductive is fixed by the time difference generation circuit 2. Thus, when a transient current flows to the power switch circuit in the preceding stage due to a load change in the logic circuit 1, this may cause the power switch circuit in the next stage to become conductive.
Transient current may flow in parallel to the plurality of power switch circuits. This results in a shortcoming in which an increase in the transient current still cannot be suppressed.